Managing the complex interconnections found in contemporary chip designs is achievable through the utilization of network-on-chip (NoC) architectures. Optimizing NoC configuration is critical for balancing reliability and latency. This paper presents a study on simultaneously optimizing NoC to improve reliability and reduce average packet latency, while considering buffer size constraints. Buffer size significantly impacts latency, cost, and reliability, making it a key element for optimization. To validate latency estimates, we compared against the Garnet2.0 simulator. Optimization utilized the NSGA-II algorithm to concurrently optimize multiple objectives like reliability and latency. The buffer size in NoC input ports constrained optimization. MATLAB was selected for implementing the algorithm due to its optimization libraries and user-friendly interface. We provide extensive findings for different NoC dimensions when subjected to both uniform and hot-spot traffic. This study contributes to designing robust, efficient on-chip communication, which is essential as computing systems demand increases.