1. When the clock frequency is 1GHz and values of resistor are 100ohm, the consumedpower is 7.43 mw and max INL i.e, become .0791 volt and for 50ohm resistor, theconsumed power is 7.43 mw as well. but INTEGRAL NON-LINEARITY(INL) become.0298 volt.
2. so, this experiment clearly shows that, if the value of resistor is decreased for sameclock frequency, the INL will be decreased as well.
3. so for 1Ghz clock frequency, if the value of resistor is low then the integralnon-linearity become low as well.
2. For clock frequency 1.2 Ghz
VDD= 5v, Low time (lt)= .4167 ns
Vref high= 4v, High time (ht)= .4167 ns
Vref low= 0v, Rise time (rt)= .1 ns
Fall time (ft)= .1 ns
INPUT PARAMETER: -
CLK = 1.2GHz
VDD = 5v
Vrefh = 4v
Vrefl = 0v
Step Size = .0625 v
Table IV: Experimental result for 1.2GHz
Time (ns)
|
values of R
|
Vout (ideal)
|
Vout (practical)
|
INL
|
INL max
|
Power
consumption
|
13.33
|
100
|
2
|
2.027
|
+.027
|
|
|
13.75
|
100
|
1.9375
|
1.8368
|
- .10
|
.10 v
|
16.98 mw
|
14.16
|
100
|
1.875
|
1.870
|
+.005
|
|
|
|
|
|
|
|
|
|
13.33
|
50
|
2
|
2.010
|
+.010
|
|
|
13.75
|
50
|
1.9375
|
1.889
|
-.0485
|
.048 v
|
19.41 mw
|
14.16
|
50
|
1.875
|
1.880
|
- .005
|
|
|
Discussion: -
1. When the clock frequency is 1.2GHz and values of resistor are 100ohm, the consumedpower is 16.98 mw and max INL i.e, become .10 volt at 13.75ns and for 50ohmresistor, the consumed power is 19.41 mw. but INTEGRAL NON-LINEARITY(INL)become .048 volt at 13.75ns.
2. so, this experiment clearly shows that, if the value of resistor is decreased for sameclock frequency, the INL will be decreased as well.
3. so for 1.2 GHz clock frequency, if the value of resistor is low then the integralnon-linearity become low as well. but the consumed power become higher forlow values of resistor i.e for R=50ohm, i.e19.41 mw
3. For clock frequency 500 Mhz
VDD= 5v, Low time (lt)= 1 ns
Vref high= 4v, High time (ft)= 1 ns
Vref low= 0v, Rise time (rt)= .1 ns
Fall time (ft)= .1 ns
INPUT PARAMETER: -
CLK = 500 MHz
VDD = 5v
Vrefh = 4v
Vrefl = 0v
Step Size = .0625 v (ideal characteristics)
Table V:Experimental result for 500Mhz
Time
(ns)
|
values of
R
|
Vout
(ideal)
|
Vout
(practical)
|
INL
|
INL
max
|
power
consumption
|
16
|
100
|
3
|
3.0027
|
+.0027
|
|
|
17
|
100
|
2.9375
|
2.9296
|
- .0079
|
.0079 v
|
6.15 mw
|
18
|
100
|
2.8750
|
2.8771
|
+.0021
|
|
|
|
|
|
|
|
|
|
8
|
50
|
3.5
|
3.5009
|
+.0009
|
|
|
9
|
50
|
3.4375
|
3.4367
|
-.0008
|
.0009 v
|
|
10
|
50
|
3.375
|
3.3756
|
+.0006
|
|
|
16
|
50
|
3
|
3.0003
|
+.0003
|
|
|
17
|
50
|
2.9375
|
2.9380
|
+.0005
|
|
6.75 mw
|
32
|
50
|
2
|
2
|
0
|
|
|
33
|
50
|
1.937
|
1.9362
|
-.0013
|
.0013 v
|
|
62
|
50
|
.1250
|
.1252
|
+.0002
|
|
|
63
|
50
|
.0625
|
. 0625
|
0
|
|
|
Discussion: -
1. When the clock frequency is 500 MHz and values of resistor are 100ohm, theconsumed power is 6.15 mw and max INL i.e., become .0079 volt at 17ns and for50ohm resistor, the consumed power is 6.75 mw. but INTEGRAL NON-LINEARITY(INL) become .0013 volt at 33 ns.
2. so, this experiment clearly shows that, if the value of resistor is decreased for sameclock frequency, the INL willbe decreased as well. 3. so for 500 MHz clock frequency, if the value ofresistor is low then the integralnon-linearity become low as well. but the consumed power become higher forlow values of resistor i.e. for R=50ohm, i.e. 6.75 mw
4. so the remaining experiment is executed for R=50ohm. for that the INLwill be less.
Table VI: Result of Proposed 6-bit DAC with different operating frequency.
process
|
150 nm
|
150 nm
|
150 nm
|
150 nm
|
150 nm
|
150 nm
|
Resolution
|
6 bit
|
6 bit
|
6 bit
|
6 bit
|
6 bit
|
6 bit
|
Speed
|
500 MHz
|
700 MHz
|
900 MHz
|
1 GHz
|
1.2 GHz
|
2 GHz
|
Power supply
|
5 volts
|
5 volts
|
5 volts
|
5 volts
|
5 volts
|
5 volts
|
Vrefh
|
4 volts
|
4 volts
|
4 volts
|
4 volts
|
4 volts
|
4 volts
|
Vrefl
|
0
|
0
|
0
|
0
|
0
|
0
|
INL max
|
.0013 v
|
.0084 v
|
.021 v
|
.0298 v
|
.0485 v
|
0.1375 v
|
Total power
consumption
|
6.75 mw
|
10.57 mw
|
10.35 mw
|
7.436 mw
|
19.41 mw
|
11.57 mw
|
Resistance
|
50 ohms
|
50 ohms
|
50 ohms
|
50 ohms
|
50 ohms
|
50 ohms
|
Maximum
settling time
|
.04 ns
|
.05 ns
|
.1 ns
|
.20 ns
|
.32 ns
|
.45 ns
|
Rise time
|
.1 ns
|
.1 ns
|
.1 ns
|
.1 ns
|
.1 ns
|
.1 ns
|
Fall time
|
.1 ns
|
.1 ns
|
.1 ns
|
.1 ns
|
.1 ns
|
.1 ns
|
low time
|
1 ns
|
.7142 ns
|
.55 ns
|
.5 ns
|
.416 ns
|
.25 ns
|
high time
|
1 ns
|
.7142 ns
|
.55 ns
|
.5 ns
|
.416 ns
|
.25 ns
|
Sample rate
|
1 GSPS
|
1.4 GSPS
|
1.8 GSPS
|
2 GSPS
|
2.4 GSPS
|
4 GSPS
|
Table VII:COMPARISON OF DAC SYSTEMS WITH OTHER PUBLISHED ARTICLE
Parameter
|
This work
|
Ref [5]
|
Ref [6]
|
Ref [7]
|
Ref [4]
|
Process(nm)
|
150
|
55
|
180
|
180
|
350
|
Supply voltage(volt)
|
5
|
--
|
1.8
|
1.8
|
3.3
|
Resolution(bits)
|
6
|
12
|
8
|
6
|
6
|
Sample rate
|
2.4 Gsps
|
3 Gsps
|
500Msps
|
300Msps
|
800Msps
|
max (LSB)
|
.0485
|
1.22
|
.024
|
0.1142
|
2.32
|
Power Consumption
|
19.41mw
|
495mw
|
5.7mw
|
944.64uw
|
165mw
|
Rload(ohm)
|
50
|
--
|
50
|
--
|
--
|