**Theory of the proposed diode physical-limit-bandwidth efficient rectification.** The conventional voltage doubler rectifier circuit7,13,16,21,22,25,26 is shown in Fig. 1(a). The basic components used in this circuit are two Schottky diodes (D1 and D2), one series pump capacitor (C1), and one shunt filter capacitor (C2), which is in parallel with the load. The functions of the pump capacitor and shunt filter capacitors are to double the peak output dc voltage and to smooth the output dc voltage by bypassing the higher-order harmonics present in the rectifier output, respectively. Figure 1(b) shows the input impedance graph of three cases: unmatched condition, conventional matching, and target matching. The maximum available bandwidth from this voltage doubler circuit is very wide from approximately 0.01 to 5.8 GHz (up to diode operating frequency 5.8 GHz), but the circuit’s input impedance seems drastically varying over the operating frequency band of the rectifier. It is expected to have flat 50 Ω real impedance and flat 0 Ω imaginary impedance over the desired frequency band and by the aid of matching narrow-band single- and/or dual-band rectifier circuit can be easily realized as shown with the conventional matching plot in Fig. 1(b). A basic requirement for wideband rectification is a lossless varying impedance matching circuit over a wideband frequency range. Indeed, this lossless variable impedance matching circuit is tough to be realized in real-time. Consequently, the wideband range of this conventional doubler circuit is limited by the designed matching circuit. Therefore, there is a tradeoff in the power conversion efficiency (PCE) of the rectifier for wideband rectifier design with the wide-band operating frequency23–37. Alternatively, we propose a novel concept for achieving efficient wideband rectification without using any external matching circuit as we explain in the succeeding paragraphs.

In the conventional voltage doubler circuit in Fig. 1(a), there is not much room to play with the input impedance except the shunt capacitor C2 and the load impedance (\({R}_{L}\)). Instead of direct grounding of diode D2 in a conventional voltage doubler circuit, a virtual dc battery was employed to investigate the input impedance of the circuit, as shown in Fig. 1(c). The input impedance of the voltage doubler circuit with virtual dc battery is shown in Fig. 1(d), which illustrates that the input impedance can be changed significantly when adjusting the dc voltage of the virtual battery. We explain this behavior by analyzing the circuit at steady state condition. At the steady state, D1 and D2 are always in reverse and forward bias condition,

This shows that we can achieve some self-matching of voltage doubler circuit by using virtual dc battery for reverse biasing on shunt diode D1 instead of direct grounding. In the actual application, there is no point in using a battery to design a rectifier circuit. Therefore, we propose an alternative way to generate a dc voltage supply to shunt diode D2 to achieve this advantage of a virtual dc battery for impedance matching on the conventional voltage doubler circuit for wideband rectifier designs.

**Proposed rectifier and virtual battery realization.** A rectifier cannot have an actual dc source or battery. So, instead, we can implement a virtual battery. This virtual battery can be formed by a secondary voltage doubler (consisting of capacitors C3 and C4, diode D3 and D4) that share the same RF input signal as shown in Fig. 2(a). The final layout mask of the proposed rectifier circuit is shown in Fig. 2(b). When the overall circuit impedance of the proposed rectifier circuit is observed with both schematic and electromagnetic (EM) simulations, it was found that this virtual dc voltage realization by additional stage of voltage doubler circuit pulls down the real part of circuit input impedance to almost 50 Ω and pulls up the imaginary part of circuit input impedance to nearly 0 Ω as presented in Fig. 2(c) and Fig. 2(d). This is because the input impedance is the function of two parallel voltage doubler circuits, and the total impedance becomes halved.

As shown in Fig. 2(a) and 2(b), a short stub transmission line (TL) is used to terminate the capacitor C4 instead of direct grounding. At low frequencies, this stub transmission line acts like a grounded inductor. But we designed this transmission line length such that it has a self-resonance around 7 GHz. Hence, at the bandwidth of interest two targeted design issues are achieved within the physical-limit bandwidth, which are (i) The real part of impedance is flattened to 50 Ω. (ii) The imaginary part of impedance is pulled to zero. When varying the stub length, the effect of this resonance on the real and imaginary parts of the input impedance of the proposed circuit is as shown in Fig. 2(c) and Fig. 2(d), respectively. When the input impedance was observed at TL = 5 mm, although this stub length provides almost perfect 50 Ω input impedance but the impedance bandwidth is only up to 2.9 GHz. We can further decrease the length of this stub to achieve an ultra-wideband response. With the stub length, TL = 2 mm, larger bandwidth up to 4.3 GHz is achievable but both the real and imaginary part input impedance deviates much from 50 Ω matching impedance. When the stub length is minimal, we can get extra wideband as compared to the long stub length but at the same time, we need to compromise with impedance matching. So, to obtain maximum flat efficiency in the entire desired wideband from this proposed rectifier, a precise selection of the short stub is necessary. Therefore, the stub length of TL = 3.5 mm was selected after the optimization, which possesses both non-fluctuating 50 Ω input impedance and larger bandwidth with minimal effect on the conversion efficiency and the output voltage.

Here we discuss about the stub to illustrate its function. The voltage waveforms at different positions of the proposed voltage doubler circuit while varying the stub length at 0.5 GHz and 3 GHz are shown in Fig. 2(e), and Fig. 2(f), respectively. At a

**Fabrication and measurement results.** A sample of the proposed diode physical-limit bandwidth rectifier was fabricated using Rogers3003™ substrate. Figure 3 shows the fabricated sample photograph and measurement setup of the proposed diode physical-limit bandwidth rectifier circuit. Then, the performance of the rectifier was verified by measuring the input reflection coefficient and the efficiency calculated from the measured output DC voltage. Measurement data were taken for a wide range of frequency, input power, and load to obtain sufficient demonstration.

The reflection coefficient (|S11|) of the fabricated rectifier was observed using the PNA Network Analyzer. Figure 4(a) shows the simulation and the measurement result of the input reflection coefficient of the fabricated rectifier at different input power levels at optimal efficiency loads. Although there is a slight change in the reflection coefficient bandwidth, the measurement result well captures the tendency of the input reflection coefficient of simulation. This change in the reflection coefficient is most possibly due to the package parasitic capacitance effect, which was not considered during simulations. From the measured reflection coefficient, it is seen that the rectifier circuit provides a reflection coefficient of less than − 10 dB over the frequency range from 0.06 GHz to 3.32 GHz, which corresponds to a calculated IBW of 192.9%. Moreover, this IBW is valid for wide range of input power level from 10 dBm to 27 dBm.

Figure 4(b) shows the simulated and measured output voltage of the fabricated rectifier. In Fig. 4(c) and (d) oscilloscope measured input and output voltage waveforms are shown for four different input powers (Pin = 5 dBm, 10 dBm, 15 dBm, and 18 dBm). The measurement maximum input power was limited by the used Tektronix digital phosphor oscilloscope (Part #DPO 70404C) measurement limit. The oscilloscope measured voltage is recorded as the voltage drop within oscilloscope internal resistance 50 Ω as shown in the measurement setup show in Fig. 3(b). Then, output voltage plotted in Fig. 4(d) was calculated as,

The measured output voltage at the instant Pin = 15 dBm at 1 GHz input power is almost exact and the oscilloscope measured output dc voltage is almost flat as can be interpreted from Fig. 4(d).

The conversion efficiency is the ratio of output DC power delivered to the load impedance RL to the power delivered by the source at the input of the rectifier circuit, which is represented by,

The rectifier conversion efficiency is computed and plotted in Fig. 5 in various conditions. The simulated maximum conversion efficiency obtained is 78.867% at 21 dBm input power with a load impedance of 1 KΩ at 1.5 GHz frequency whereas the measured maximum conversion efficiency obtained is 77.3% at 23 dBm input power with a load impedance of 1.3 KΩ at 0.9 GHz frequency. The conversion efficiency over the operating frequency bandwidth with different input power levels at optimal efficiency loads is shown in Fig. 5(b). The efficiency remains above 50% throughout the entire IBW from 0.06 to 3.32 GHz at input power levels from 10 dBm to 27dBm. For the input power of 20 dBm to 23 dBm, the conversion efficiency remains above 70% at the frequency range 0.06 to 1.82 GHz. The calculated efficiency bandwidth (EBW) is 187.23% (maintaining conversion efficiency > 70%) whereas 192.9% (maintaining conversion efficiency > 50%), which is the highest ever recorded than other reported wideband rectifiers23 − 37. Moreover, the efficiency over the entire operating bandwidth has negligible fluctuations.

The simulated and measured conversion efficiencies at different loads with optimal efficiency input power over the operating frequency bandwidth is presented in Fig. 5(c), whereas over the varying load at different input power levels at optimal efficiency frequency is presented in Fig. 5(d). From these graphs, it can be interpreted that the proposed rectifier supports a wide range of loads while maintaining a maximum flat efficiency.