A. Optimization of standby voltages
Figure 3(a) shows two possible approaches to program a cell. In both approaches, the cathode voltage (VC) is defined as 0.0 V. However, the voltage differences between the gate and the cathode in the standby state (VGC,ST) are set to two different values. -0.4 V (right) is the optimized value, while 0.0 V (left) is the conventional case for a comparison. The device with the VGC,ST of -0.4 V has a low program anode-cathode voltage (VAC,P) of 1.2 V, and this is only a half of VAC,P required when VGC,ST is 0.0 V. This low VAC,P is attributed to the accumulated holes in p-base by the negative VGC,ST. When the VGC rapidly rises to 0.4 V for a program operation, the accumulated holes by the negative VGC,ST (-0.4 V) reduce the energy band barrier height in the p-base (HP). As such, the device with the optimized VGC,ST minimizes the power consumption in program operation since a smaller VAC,P is required to reduce the HP. Figure 3(b) shows the stored hole density in the p-base (NP) as a function of standby time at state-1 (TST,1) after the program pulse. As the TST,1 increases, the NP decreases due to the carrier recombination at the junctions. Due to the low VAC,P, the device with VGC,ST of -0.4 V exhibits lower NP than the case of 0.0 V in the early stage (TST,1 < 10 µs). However, the NP in the later stage (TST,1 > 10 s) is higher than the case of 0.0 V. This higher NP is the result of the low recombination rate caused by the depletion of electrons in the p-base due to the negative VGC,ST. Figure 3(c) shows the energy band diagrams of 3-T TRAM at 10 ms after a program pulse to investigate the data retention characteristic depending on VGC,ST. The left side is for VGC,ST = 0.0 V, and the right side is for VGC,ST = -0.4 V. The HP difference between the state-0 and state-1 at 10 ms after a program pulse exhibits a high value of 0.17 eV with the optimized VGC,ST of -0.4 V due to the long-lasting NP. This indicates that the device with an optimized VGC,ST has an improved data retention characteristics that can maintain the low-resistance state (state-1) for a longer time.
Figure 4(a) shows IA-VAC characteristics for the VAC pulse with Trise of 1000 s, Thold of 2 ns, and Tfall of 1000 s when VGC is fixed at -0.4 V. It has been previously reported that the IA-VAC curve with long Tfall of 1000 s can effectively provide a minimum VAC,ST to improve the data retention characteristics . When VGC is fixed to -0.4 V, the device exhibits a rapid increase of IA at VAC = 2.65 V representing a switching from the state-0 to the state-1. This indicates that a higher VAC is required to switch the state as long as VGC is maintained below − 0.4 V, and thus the state is well protected. As mentioned above, for a normal programing, only 1.2 V of VAC,P is required since VGC is increased from − 0.4 V to 0.4 V. As such, for VAC,P less than 2.65V applied to the bit-line (BL) in array operation, 3-T TRAM can avoid unwanted program errors if the voltage of the word-line (WL) is fixed to VGC,ST = -0.4 V or below.
In the downward VAC sweep (Tfall), the switching of the state occurs at 0.56 V as evidenced by the sharp slope (red dashed line in Fig. 4(a)). Thus, the state-1 can be maintained at VAC,ST of 0.56 V. To investigate this drastic change by the voltage difference as small as 0.1 V, NP as a function of TST,1 is examined for two different VAC,ST of 0.5 V and 0.6 V (Fig. 4(b)). For VAC,ST = 0.5 V, the stored holes disappear rapidly after 10 µs, but for VAC,ST = 0.6 V, the device can maintain a high NP of about 1.47×1018 cm− 3 for more than 10 s which is 106 times larger. Figure 4(c) shows the energy band diagrams of 3-T TRAM at TST,1 =10 s for two different VAC,ST of 0.5 V and 0.6 V. With VAC,ST of 0.6 V, holes more than the amount of recombination are injected into the base region, and the state-1 band shape along with the stored charge is maintained. With VAC,ST of 0.5 V, on the other hand, the holes injection is not enough to compensate the loss of holes by recombination, and the stored charge rapidly disaapear, returning the band shape back to that of the state-0. A device with VAC,ST lower than 0.5 V will face similar level or faster charge loss. Considering the clock speed of modern VLSI circuit, the 3-T TRAM with VAC.ST of 0.6 V can exhibit the continuous state-1 virtually without a refresh operation. In addition, despite the high VAC,ST of 0.6 V, the device has a standby current as low as 1.14 pA, suggesting that the 3-T TRAM with the VAC,ST of 0.6 V is suitable for a low-power operation.
B. Memory Operation of 3-T TRAM array
Compared to the 2-T TRAM without the gate terminal, the 3-T TRAM has a strong state immunity against the change of anode-cathode potential due to the gate terminal. On the other hand, the shift in gate-cathode potential in the 3-T TRAM easily interferes with the stored information. This disturbance is studied by assuming an operation pulse applied to a nearby cell. The cell under the study is initially at unselected bias condition, and the subject cell's states after the disturbance are observed. Figure 5 shows the schematic of a memory-cell-array configuration of 3-T TRAM. Our study shows that, with a proper operating scheme (maintaining fixed VGC to the unselected cells), this memory-cell-array configuration can prevent unselected cells' unwanted changes. For an efficient adjustment of VGC in the memory operation, the gate and cathode electrodes are set to the WL and BL, respectively. The anode electrode is fixed at 0.6 V. Table. 1 shows the operating voltage conditions for the 3-T TRAM array. To maintain the stable state-0 and state-1 in the standby state, VG and VC in the standby state are set to -0.4 V and 0.0 V with the VA of 0.6 V. The operation strategies to prevent the array disturbance, found through our study, are summarized for each operation (Program, Erase, and Parallel Read) as the followings.
Program: To program the selected cell, the selected VC decreases from 0.0 V to -0.8 V as shown in Table 1. This decreased VC can facilitate the influx of carriers into the base region. As such, the selected cell is programmed with the VGC of 0.4 V and VAC of 1.4 V. Figure 6(a) shows the simulated energy band diagrams of the cell under programming at TST,0 and TST,1 = 10 s. The selected cell for the program operation can maintain the state-1 with low HP even at the high TST,1 of 10 s. However, the problem with the above approach is that all cells in the selected BL experience unwanted program operation by the VGC of 0.4 V and VAC of 1.4 V, which are larger than the VGC of 0.4 V and VAC,P of 1.2 V, respectively. To prevent this unwanted programming, VG in all WLs except for the selected WL can be decreased from − 0.4 V to -1.2 V. In this way, the VGC can be recovered back to -0.4 V from 0.4 V. Figure 6(b) shows the simulated energy band diagrams of the unselected cells at TST,0 and TST,1 = 0 s. The unselected cells exhibit no change in energy band with the VAC of 1.4 V if VGC is below − 0.4 V. Thus, the selected cell exhibits the continuous state-1, while the unselected cells can avoid the unwanted program disturbance.
Erase: To erase a selected cell, the VG and VC of the selected WL and BL should be increased from − 0.4 V to 0.8 V and 0.0 V to 0.4 V, respectively, as shown in Table 1. In Fig. 7(a), the NP is investigated as a function of TST,0 after the erase operation at TST,1 of 2.5 ns. The NP is decreased due to the depletion of stored holes in the p-base as the VGC increases from − 0.4 V to 0.4 V. Also, the hole injection into the p-base during the erase operation is restrained by decreasing VAC from 0.6 V to 0.2 V. As the TST,0 increases, the NP is back to 0 cm− 3, which represents the complete state-0. To investigate the reason, the energy band diagram at TST,0 of 2.5 ns is examined and compares with the energy band at TST,1 of 2.5 ns (Fig. 7(b)). After the erase operation, the n-base (HN) energy band height decreases as the HP increases. The holes in the anode flow into the p-base over the lowered HN, and the NP increases. The number of injected holes decreases due to the increased HN by the recombination process, so the NP saturates at 0 cm− 3 as TST,0 increases. From this result, it is found that the cell selected for the erase operation can exhibit the state-0 with the sufficiently high HP at any TST,0. However, the erasing method with the increased VGC of the selected WL can cause a problem of erasing all cells on the same WL. To avoid this issue, the VGC should be reduced from 0.4 V to -0.4 V by increasing VC from 0.0 V to 1.2 V on all BLs except for the selected BL (Table 1). Accordingly, the erase disturbance pulse with VAC = -0.6 V and VGC = -0.4 V applies to the unselected cells on the same WL. The state-1 should be detectable at any time even if this erase disturbance pulse is repeated after the NP is saturated to the lowest value of 1.47×1018 cm− 3. To confirm this, as shown in Fig. 7(c), the NP is examined as a function of the number of this erase disturbance pulse. Despite the repeated disturbance pulses, NP exhibits a negligible decrease near 1.1×1018 cm− 3 so that the device can maintain the state-1. In addition, the slightly reduced NP can readily return to its original state-1 by applying read operation. Therefore, the 3-T TRAM can overcome the erase disturbance by controlling the VGC in unselected cells.
Parallel Read: To perform the parallel read operations on the cells that share the same BL, the VC of the selected BL and the VG of all WLs are set to -0.8 V (Table 1). If the VC in the selected BL is decreased to -0.8 V, not only VAC increases to 1.4 V but also VGC increases to 0.4 V. This high VGC lowers the HP and causes unwanted program errors of the cells in the selected BL. To avoid this, the VG in all WLs should be decreased to -0.8 V so that 0.0 V of VGC and 1.4 V of VAC are applied to the cells in the selected BL. To investigate the effect of the read operation on the state-0, the operating voltage and anode current are extracted after ten consecutive read operations are applied following an erase operation as shown in Fig. 8(a). Although the ten continuous read pulses are applied to the device after the erase operation, the read current gradually decreases, confirming that the state-0 stably is maintained. This result indicates that the 3-T TRAM with the suggested array configuration for reading exhibits a reliable disturbance immunity for the state-0. Additionally, to confirm the detectability of the state-1, the operating voltage and anode current for a program and a read with the TST,1 of 10 s are extracted (Fig. 8(b)). The read pulse can detect the state-1 continuously with a high current even at a long TST,1 of 10 s.