Well-aligned CNT arrays were CVD-grown on ST-cut quartz substrates using Fe nanoparticles as catalyst (Fig. S1). Deposited via electron beam evaporation (EBE), the Fe nanoparticles in the catalyst stripes were randomly positioned and had different sizes owing to the statistical nature of the EBE process. In addition, the nucleation through the vapor-liquid-solid processes (VLS) is also stochastic; therefore, CNT arrays were randomly distributed perpendicular to the growth direction defined by the gas flow in terms of both chirality and position (Figs. S2 and S3), which is highly unwanted for high-performance electronics applications37-39. As shown in Fig. 1a, FETs fabricated on such CNT arrays have three distinct channel types with no CNTs or open channel (O), with pure semiconducting CNTs (S) and with at least one metallic CNT (M). These different channel types lead to distinguishable electronic characteristics, i.e. O channel with very low current, conducting channel with large current on/off ratio (S channel) and small on/off ratio (M channel with metallic CNT). Since the location and type of CNTs in the channel are determined by the stochastic nucleation and random catalyst distribution, FETs fabricated on the CNT arrays (defined by the source/drain contacts) will show O, S, and M characteristics in a random manner perpendicular to the growth direction. The random nature neither predictable unclonable; therefore, in principle one row of FETs meets the requirement of PUFs. Induced by the quartz lattice-CNT interaction40, CNT arrays grew along the [2 -1 -1 0] crystal orientation for several hundred microns41, which ensured that the properties of CNT arrays were identical parallel to the growth direction. As shown in Fig. 1b, two rows of FETs fabricated in parallel on the same CNT array show O, S, and M types with the same order, so two identical PUFs can be fabricated together.
To fabricate FETs, CNT arrays were transferred using PMMA as a medium to the target Si/SiO2 substrate before device fabrication42, and the substrate served as the global back gate to measure the transfer characteristic characteristics. Pd films were deposited as the source/drain contacts to form p-type FETs with a channel length (Lch) of 1 μm and variable channel width (Wch) controlled by the contact width and etched area, as shown in Fig. 2a. The test units of CNT twin PUFs were designed to be 2×24 or 24 pairs of FETs with an equal spacing of 5 μm, and all FETs were connected to peripheral on-chip pads, as shown in Fig. 2b and Fig. S4. According to the patterned catalyst stripes with a 0.25 mm distance and the pad settings, the test units were batch fabricated in the form of a matrix with a 0.5 mm distance (Fig. 2c and Fig. S4).
We measured the transfer characteristics of three typical pairs of FETs in a test unit with a drain-to-source voltage (Vds) of -1.0 V (Fig. 2d). The FETs with no CNTs in the channel exhibited an on-state current (Ion) below 1 pA, while the FETs with CNTs in the channel showed an Ion far above 1 μA. Among conducting FETs, the FETs with only semiconducting CNTs showed an on/off ratio of up to 6 decades, while those having at least one metallic CNT showed an on/off ratio of less than 10. Because they were fabricated on the same CNT array, those FETs pairs with the same order from the two rows of FETs showed transfer characteristics that almost coincide, indicating that they were identical. Five hundred FETs on CNT arrays were readily classified into these three types of O, S and M devices according to their extracted on state current Ion and current on/off ratio, by defining O-type FETs be the one with Ion below 0.1 nA, S-type FETs with Ion above 0.1 nA and an on/off ratio greater than 50, and M-type FETs with Ion above 0.1 nA and an on/off ratio of less than 100 (Fig. 2e and Fig. S5)
To utilize CNT PUFs to generate ternary bits and thus keys with maximum randomness and entropy, O-, S- and M-type FETs should be tuned to have an equal occurrence probability of 1/3, which is realized by tuning the CNT arrays density and FET channel width Wch . As shown in Fig. 2f, we extracted CNT positions from SEM images of CNT arrays and then calculated the tube-to-tube spacing (CNT pitch). Through statistical distribution fitting, the CNT pitches (CPs) were found to meet the lognormal distribution, which was verified by other CNT samples we grew with different densities and those published by other groups38, 43 (Fig. 2g and Fig. S6). According to the simulation with a CP of 1±0.5 μm and an ideal metallic/semiconducting CNT ratio (MSR) of 1/2, Fig. 2h shows that the ratio of O-type FET decreases and M-type FETs increases with increasing Wch, while the ratio of S-type FET first increase and then decrease (see also Fig. S4). The nonmonotonic change in the ratio of S-type FETs results from the fact that the possibility of metallic CNTs appearing in the S-type channel increases rapidly when Wch exceeds 1 μm, which effectively turns the S-type FET into a M-type FET (Fig. S7).
We define the minimal difference (MD) as the sum of the square difference between the ratios of O-, S- and M-type FETs, and assume an ideal value (1/3) for given CP and MSR to maximize randomness. When Wch is set to 0.8 μm, MD is 0.03, with O, S, and M ratios of 0.4, 0.4 and 0.2; therefore, the ratio of S-type FETs needs to be decreased, which can be realized by two strategies. One is to increase the MSR to increase M-type FETs (Fig. S8), and the other is to increase the deviation in the CP to increase mixed FETs (Fig. S9). The MSR can be adjusted by many factors, including catalyst, carbon source, atmosphere, and electromagnetic field44, 45, while CP is mainly determined by the distribution of Fe nanoparticles. Through co-optimization of CP and MSR, MD is reduced down to 10-4 (Fig. S10). Finally, CNT arrays with a CP of 0.65±0.58 μm and an MSR of approximately 0.4 (Fig. S11) were selected to demonstrate CNT twin PUFs with ideal ternary bits, and the experimental result is in good agreement with simulation (Fig. 2h). A total of 1600 FETs with a Wch of 600 nm were fabricated to generate a 40×40 ternary bit map (Fig. 2i), in which 532, 516, and 552 O-, S- and M-bits were counted, respectively.