The evolution of the components embedded on a single chip is growing faster day by day, resulting in a considerable impact on the performance metrics and communication between the cores in the NoC architecture. So, to overcome such issues, it is important to provide an efficient mapping between the cores, such that the communication between them increases. To improve the performance of a network, throughput and latency also play a significant role. In this research paper, an efficient mapping strategy implemented on the real-time embedded applications named ERTEAM. In this algorithm, based on the minimum Core Average Distance (CAD) the mapping region is finalized, ensuring the overall mapping area reduced. The PE’s mapped according to the minimum communication energy in the selected mapping region. This research evaluated a set of embedded applications, which reveals a reduction in latency at 12.3% against BBPCR and 8.4% against SBMAP. The simulation time reduces at an average of 19% against BBPCR and 9.6% against SBMAP. The throughput increases at an average of 14.5% against BBPCR and 7.8% against SBMAP and reduces the communication energy by 15.6% against BBPCR and 5.2% against SBMAP.