Typical current oscillation characteristics as a function of *V*B are presented in Fig. 2 for two SEDs which will be named Device A and Device B in this report. In both the graphs shown in this figure, three *I*D–*V*B curves at the *V*T values of 1.8, 10, and 20 V are superposed. The observed oscillation curves are clear, and they originate from a single dot, as discussed in our previous study37. The oscillation period was approximately 27 (Device A) or 37 V (Device B) corresponding to the back-gate capacitance *C*B of 0.0059 (Device A) or 0.0043 aF (Device B), respectively. Because *C*B of Device B is smaller, the dot contributing the current oscillation in this device should be smaller than that of Device A. In both devices, the current oscillations were added to the constant background current components (~520 pA (Device A) and ~1.0 nA (Device B)), which were attributed to the parallel conductive paths comprising the dots with the Coulomb blockade lifted. Such dots attributing to the background current are considered relatively large and/or have higher tunneling conductance than the quantized value (2*e*2/*h*)37. By comparing the *I*D–*V*B curves with different *V*T values, a systematic shift in the current peak was identified. With increasing *V*T values, the peak around 20 V for Device A gradually shifted to 14 and 3.3 V (Fig. 2a). Similar tendency was seen in Fig. 2b for Device B with a peak shift from 22 to 16 and then to 9.3 V. These peak shifts toward the negative *V*B direction demonstrated that the current oscillation characteristics can be controlled by both the top and back gates even in the metal multidot SED, where the change in the nanodot charging state by *V*T can be compensated by *V*B and vice versa.

To clearly understand the details of the peak shift as a function of the two gate voltages, *V*T and *V*B, a contour plot of drain current was employed27. For this purpose, numbers of *I*D–*V*B curves were measured using various *V*T values from 0 to 30 V in 300 mV steps, where the *V*B sweep was conducted in the sequences of 0–30 V, 30–−30 V and −30–0 V. The current oscillations were well reproducible for the back-and-forth *V*B sweeps. In addition, they were satisfactory stable over a few days against the peak shift due to charge offset drift, similar to the findings of a previous study38. The data measured from *V*B = 30 to −30 V are plotted in Fig. 3a and 3b as two-dimensional (2D) contour maps of the drain current corresponding to the stability diagrams of the device. The current peaks shown in bright contrast are systematically shifted. That is, the phase of the current oscillation can be controlled using *V*T and *V*B. These contour maps are simple and periodic, as indicated by the yellow dotted lines, although there is an irregularity in Fig. 3b at *V*T = 17 V, which is caused by charge noise that may be attributed to the effect of satellite nanodots acting as the single-electron traps37. These characteristics can confirm that the major current oscillation certainly originates from a single dot37. Controllability of the charge state of the single dot by the double-gate is clearly confirmed despite the multidot structure. The investigation of linear peak shift dependence on the *V*B and *V*T values in the complex nanodot array conducted in this study is unprecedented and important, and it has been discussed using multigate SEDs with a simple dot configuration28,39,40 concerning the logic operation. The results shown in Fig. 3 suggest that the SEDs comprising randomly dispersed metal multidots can operate as two-input logic-gate devices.

Here, the stability diagrams are analyzed to understand the characteristics of the randomly dispersed nanodot system. For the devices investigated in this study, the top and back gates are capacitively coupled to the SED and the current peak shift according to the *V*B and *V*T values follows the equation given below:

$${C}_{\text{B}}{V}_{\text{B}}+ {C}_{\text{T}}{V}_{\text{T}}=const, \left(1\right)$$

where *C*B and *C*T are the capacitances between the single dot and back/top gates, respectively. When *V*T changes by Δ*V*T, the peak shift in the current oscillation (Δ*V*B) is given by the following equation39:

$${ \varDelta V}_{\text{B}}= - ({C}_{\text{T}}/{C}_{\text{B}}){{\Delta }V}_{\text{T}}$$

2

.

Therefore, the gate capacitance ratio *C*B/*C*T of the dot is given as − Δ*V*T/Δ*V*B, which is evaluated using the slope of the observed current peak line presented in the contour map40–44. Using Figs. 3a and 3b, the gate capacitance ratio *C*B/*C*T between the single dot and back/top gates was evaluated as ~1.2 (Device A) or ~2.0 (Device B). Therefore, using the *C*B value described above, *C*T was given as ~0.0049 (Device A) or ~0.0022 aF (Device B). These results are plotted in Fig. 4 with data from two other devices. For the device structure investigated in this study, the back-gate insulator comprised 200-nm-thick SiO2 and the top-gate insulator comprised 45-nm-thick MgF2 and 300-nm-thick SiO2. Assuming the parallel-plate capacitor structure and bulk dielectric constants (3.8 for SiO2 and 5.2 for MgF2)45, the capacitance ratio *C*B/*C*T is ~1.7, as shown in Fig. 4. For a total set of devices, the evaluated *C*B/*C*T followed this relation. Furthermore, each *C*B/*C*T ratio was between 1.2 and 2.7, showing clear discrepancy from this rough estimation using the parallel-plane model. This discrepancy was caused by the geometric factors of the dot array, such as nanodot shape and the arrangement of dots. In the following paragraphs, this is discussed using a simple model.

The nanodot-array SED comprises numerous dots with various sizes. Because dots are formed on the substrate plane, the planar arrangement of hemispheric nanodots can be assumed as a model for this discussion. In addition, for easy calculations, the model was simplified into parallelly arranged half-columnar dots with infinitive axis length. An example of the cross-sectional schematic is presented in Fig. 5 where the column axis of the dot is perpendicular to the paper surface. The dot is half-circular in this diagram (gray), and it will be called the half-circular dot in the following discussion. By adopting this model, we only require 2D electric field calculations with less parameters. A compact software (EStat) based on the finite element method was used to simulate the electric field and evaluate the capacitances (per unit length along the column axis) between the dot and top/back-gate electrodes. Although the model was simplified, the simulation results must provide the intrinsic features of the nanodot array. In the next paragraph, the simulation results are explained with details of the model.

A typical model for evaluation is shown in Fig. 5. Notably, the horizontal and vertical magnifications of this diagram are different from each other. The in-plane diameter of the metallic half-circular dot is 30, 20, or 14 nm, referred to as *L* (large), *M* (medium), or *S* (small), respectively, throughout this report. They are arranged horizontally to form a dot array. In Fig. 5, the dot arrangement is called *LSL* in the central part and *M* in other regions. The distance between the adjacent dot edges was kept constant at 10 nm. The dots are sandwiched between two 100-nm-thick SiO2 layers acting as the top and back-gate insulators. On the surface of these SiO2 layers, two metallic gates (gray) are attached. For simulations, one of the gate electrodes was biased by 1 V, while the dots and another electrode were grounded. Simulated potential distributions are shown in Fig. 5 as color maps, and the lines of the electric force are represented by white lines. As described below, remarkable difference is observed between Fig. 5a for voltage application to the top gate and Fig. 5b for voltage application to the back gate. The electric force lines shown in Fig. 5b are almost parallel like those in a parallel capacitor, except near the dot edges. Thus, *C*B of each dot must be almost proportional to the dot size. Conversely, in Fig. 5a, the electric force lines are strongly curved and those near the central *S* dot are attracted by the adjacent *L* dots. Some of them are absorbed by the *L* dots; therefore, *C*T of the central *S* dot becomes smaller in this dot arrangement while *C*T of the *L* dot becomes larger. This is because of the geometrical difference between the upper (roundish) and lower (flat) dot surfaces. The dot shape in the nanometer scale can modulate the electric field, changing the charge distribution on the dot surface and capacitance with the gate electrode. This suggests that the Coulomb blockade oscillation characteristics in the multidot SED comprising the complicated dot array are expected to be modulated by the shape and distribution of the dots, including the surrounding dots.

These simulations were performed for various dot arrangements, and the gate capacitance ratios *C*B/*C*T of the central dots were evaluated. Examples of the *SSS*, *MSM*, and *LSL* arrangements are plotted in Fig. 6. To check the applicability of the calculations, simulation results of circular dots with the same arrangements are superposed in the graph. Because the dots are symmetric in this case, the *C*B/*C*T ratio should be 1.0 in all the cases, reflecting the thickness ratio of the top (100-nm-thick) and bottom (100-nm-thick) insulating layers. The simulation results fit well with this value. Considering the half-circular dots, the *C*B/*C*T value shows a large change from 0.95 to 1.27 depending on the adjacent dot size. This is because of the nonuniform distribution of the electric field between the top and bottom gates, which is attributed to the geometrical shape effect of the central dot and surrounding dots (Fig. 5). In the *SSS* arrangement, for example, the roundish shape of the surface facing the top gate gathers the electric force lines rather than the flat surface facing the bottom electrode. Therefore, *C*T becomes larger than *C*B and *C*B/*C*T is <1. For the large adjacent dot, as in the *MSM* arrangement, some electric force lines are attracted by the *M* dots, making the *C*T value small, ultimately resulting in *C*B/*C*T of >1. Lager adjacent dots in *LSL* attract the electric force lines very much from the *S* dot, and the deviation of *C*B/*C*T from 1 becomes large. Similar results were also identified for *M* or *L* as the central dot. These fundamental discussions using 2D simulations must also be valid for the three-dimensional dot shape and arrangement. Geometrical factors of the multidot system resulted in the variation of the *C*B/*C*T value from the average value (Fig. 4).