Fig. 2(a)-(d) depicts the numerical computation of drain current, output conductance, transconductance generation factor, and intrinsic gain respectively for different values of tox. It is obvious from Fig. 2(a) that in weak inversion region of III-V channel material FET for lower values of (gate-source voltage) VGS as tox is reduced; drain current is also reduced due to the reduction in gate capacitance caused due to the influence of quantum capacitance. Fig. 2(b) depicts the computation of output conductance (gd) in respect of different thickness of the oxide layer. As oxide thickness increases output conductance increases resulting in lower output resistance thereby reducing the gain of the device. Fig. 2(b) indicates that the pinnacle value of gd decreases by 15.21% when tox is reduced to 1 nm from 2.5 nm for Si channel material at (drain-source voltage) VDS=0 V. The pinnacle value of gd shifts from VDS=0.66 to VDS=0.64 V and pinnacle value enhances by 6.73% when tox is reduced from 2.5 nm to 1 nm for III-V channel material SG-FET. Fig. 2(c) depicts the computation of TGF in respect of gate voltage for different values of tox. Fig. 2(c) indicates that TGF is higher at lower values of tox for both III-V and Si channel material SG-FET. The magnitude of transconductance (gm1) and drain current (ID) increases when oxide thickness (tox) is reduced for III-V channel material surrounding-gate FET. The transconductance generation factor (TGF) is expressed as the ratio of gm1 and ID. So, TGF increases when tox is reduced. The pinnacle value of TGF reduces by 13.96% when tox is enhanced from 2.5 nm to 1 nm oxide thickness for Si channel material based SG-FET. Fig. 2(d) depicts the computation of intrinsic gain (dB) and it is obvious that intrinsic gain is higher at lower values of tox for both devices. The pinnacle value of intrinsic gain reduces by 27.6% when thickness of oxide layer is enhanced from 1 to 2.5 nm for Si channel material SG-FET. The lower value of output conductance is desirable to achieve higher gain.
Fig. 3(a) depicts the variation of drain current in respect of VGS, and it is obvious that the pinnacle magnitude of drain current enhances by 5.31% and 78.39% when CL decreases from 50 to 20 nm for III-V and Si channel material respectively at VGS=1.08 V. The drain current is proportional (inversely) to CL, hence it is noticed that as CL reduces, the drain current increases for both Si and III-V channel material devices. So, lower channel length yields a higher drain current. Fig. 3(b) depicts the calculation of gd in respect of VDS for different channel length. As channel length reduces, output resistance decreases and output conductance increases. It is obvious from Fig. 3(b) that gd is higher for lower values of channel length for both III-V and Si channel material SG-FET. Fig. 3(c) depicts the calculation of TGF in respect of VGS for different channel length. As CL reduces, the drain current and transconductance increases and consequently TGF reduces. It can be concluded from Fig. 3(c) that as channel length enhances, TGF is also increased. It is evident from Fig. 3(c) that the pinnacle value of TGF reduces by 2.19% at VGS=0.14 V and 9.17% at VGS=0 V when the channel length is decreased from 50 to 20 nm for III-V and Si channel material respectively. Fig. 3(d) depicts the computation of intrinsic gain (dB) for different channel length. As CL reduces, the transconductance and output conductance increases. It is evident against Fig. 3(d) that higher channel length results in a greater magnitude of intrinsic gain.
The variation of the drain current in respect of VGS for dissimilar magnitudes of channel height at VDS of 1 V is represented by Fig. 4(a). The drain current reduces due to the reduction in the cross-sectional area for the flow of charge carriers when the height of the channel is reduced. It is obvious from Fig. 4(a) that the pinnacle magnitude of drain current reduces by 46.57% and 32.9% when H is reduced from 18 to 10 nm for III-V and Si channel material respectively at VGS=1.08 V. Fig. 4(b) depicts the variation of gd in respect of VDS for dissimilar channel height. The output conductance enhances as channel height increases causing a decrease in the output resistance. It is obvious from Fig. 4(b) that higher channel height yields higher output conductance for both III-V and Si channel material SG-FET. Fig. 4(c) depicts the calculation of TGF in respect of VGS for dissimilar magnitude of H. It is obvious from Fig. 4(c) that the lower magnitude of H yields a higher value of TGF. TGF is almost constant at lower values of VGS and reduces as VGS reduces. Fig. 4(d) depicts the computation of intrinsic gain (dB) for dissimilar channel height, and it is obvious that lower channel height yields higher intrinsic gain in III-V and Si channel material SG-FET.
Fig. 5(a) depicts the variation of drain current in respect of VGS, and it is obvious that the pinnacle value of drain current reduces by 22.83% and 44.52% when Nd is decreased from 1x1019 to 5x1018 cm-3 for III-V and Si channel material SG-FET respectively at VGS=1.08 V. Fig. 5(b) depicts the computation of output conductance in respect of VDS for dissimilar magnitude of Nd. As Nd increases output conductance also enhances resulting in decreasing output resistance. Fig. 5(c) depicts the calculation of TGF in respect of VGS for dissimilar magnitude of Nd. The intrinsic gain and TGF both reduces with increase in magnitude of Nd. The pinnacle value of TGF is reduced by 21.96% when doping concentration is increased from 5x1018 to 1x1019 cm-3 for Si channel material SG-FET. Fig. 5(d) depicts the calculation of intrinsic gain in respect of VGS for dissimilar magnitude of Nd.
The dynamic power dissipation (PD) is the product of clock frequency (fp), load capacitance (CL), and square of the supply voltage (VDD). The PD can be reduced by reducing any of the three parameters among fp, CL, and VDD. The problem associated with the reduction of fp is increased time delay. The second approach is to reduce CL, but it involves system design so that system components such as wires and the number of pins are reduced, and fan-out is minimized. Another generic approach is to reduce the supply voltage VDD; which is possible only through device technology.
Fig. 6 depicts the computation of dynamic power dissipation at VDS=1 V and 1 MHz frequency. Fig. 6(a) depicts the variation of PD in respect of VGS for different magnitudes of CL. The pinnacle magnitude of PD reduces by 65.35% when CL is decreased from 50 to 20 nm for III-V channel material at VGS=1.08 V. The pinnacle magnitude of PD shifts from VGS=1.08 V to VGS=1.02 V and pinnacle magnitude decreases by 69.50% when CL is decreased from 50 to 20 nm for Si. The magnitude of PD in Si is noticed to be higher than III-V channel material for 50 nm and 20 nm channel lengths. Fig. 6(b) depicts the variation of PD in respect of VGS for different channel height. The magnitude of PD in III-V channel material is less as compared to Si for 18 nm and 10 nm channel height. Fig. 6(c) depicts the variation of PD in respect of VGS for different values of tox. The magnitude of dynamic power dissipation in III-V channel material is less than Si.